summaryrefslogtreecommitdiff
path: root/usr/src/dkms_source_tree/hda_intel.c
diff options
context:
space:
mode:
Diffstat (limited to 'usr/src/dkms_source_tree/hda_intel.c')
-rw-r--r--usr/src/dkms_source_tree/hda_intel.c2849
1 files changed, 2849 insertions, 0 deletions
diff --git a/usr/src/dkms_source_tree/hda_intel.c b/usr/src/dkms_source_tree/hda_intel.c
new file mode 100644
index 0000000..05a0a40
--- /dev/null
+++ b/usr/src/dkms_source_tree/hda_intel.c
@@ -0,0 +1,2849 @@
1/*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/dma-mapping.h>
43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
47#include <linux/mutex.h>
48#include <linux/reboot.h>
49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61static int probe_only[SNDRV_CARDS];
62static int single_cmd;
63static int enable_msi = -1;
64#ifdef CONFIG_SND_HDA_PATCH_LOADER
65static char *patch[SNDRV_CARDS];
66#endif
67#ifdef CONFIG_SND_HDA_INPUT_BEEP
68static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70#endif
71
72module_param_array(index, int, NULL, 0444);
73MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
74module_param_array(id, charp, NULL, 0444);
75MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
76module_param_array(enable, bool, NULL, 0444);
77MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78module_param_array(model, charp, NULL, 0444);
79MODULE_PARM_DESC(model, "Use the given board model.");
80module_param_array(position_fix, int, NULL, 0444);
81MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
82 "(0 = auto, 1 = none, 2 = POSBUF).");
83module_param_array(bdl_pos_adj, int, NULL, 0644);
84MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
85module_param_array(probe_mask, int, NULL, 0444);
86MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
87module_param_array(probe_only, int, NULL, 0444);
88MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
89module_param(single_cmd, bool, 0444);
90MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
92module_param(enable_msi, int, 0444);
93MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
94#ifdef CONFIG_SND_HDA_PATCH_LOADER
95module_param_array(patch, charp, NULL, 0444);
96MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97#endif
98#ifdef CONFIG_SND_HDA_INPUT_BEEP
99module_param_array(beep_mode, int, NULL, 0444);
100MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102#endif
103
104#ifdef CONFIG_SND_HDA_POWER_SAVE
105static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106module_param(power_save, int, 0644);
107MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
109
110/* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114static int power_save_controller = 1;
115module_param(power_save_controller, bool, 0644);
116MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117#endif
118
119MODULE_LICENSE("GPL");
120MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
122 "{Intel, ICH7},"
123 "{Intel, ESB2},"
124 "{Intel, ICH8},"
125 "{Intel, ICH9},"
126 "{Intel, ICH10},"
127 "{Intel, PCH},"
128 "{Intel, CPT},"
129 "{Intel, SCH},"
130 "{ATI, SB450},"
131 "{ATI, SB600},"
132 "{ATI, RS600},"
133 "{ATI, RS690},"
134 "{ATI, RS780},"
135 "{ATI, R600},"
136 "{ATI, RV630},"
137 "{ATI, RV610},"
138 "{ATI, RV670},"
139 "{ATI, RV635},"
140 "{ATI, RV620},"
141 "{ATI, RV770},"
142 "{VIA, VT8251},"
143 "{VIA, VT8237A},"
144 "{SiS, SIS966},"
145 "{ULI, M5461}}");
146MODULE_DESCRIPTION("Intel HDA driver");
147
148#ifdef CONFIG_SND_VERBOSE_PRINTK
149#define SFX /* nop */
150#else
151#define SFX "hda-intel: "
152#endif
153
154/*
155 * registers
156 */
157#define ICH6_REG_GCAP 0x00
158#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
159#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
160#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
161#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
162#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
163#define ICH6_REG_VMIN 0x02
164#define ICH6_REG_VMAJ 0x03
165#define ICH6_REG_OUTPAY 0x04
166#define ICH6_REG_INPAY 0x06
167#define ICH6_REG_GCTL 0x08
168#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
169#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
170#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
171#define ICH6_REG_WAKEEN 0x0c
172#define ICH6_REG_STATESTS 0x0e
173#define ICH6_REG_GSTS 0x10
174#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
175#define ICH6_REG_INTCTL 0x20
176#define ICH6_REG_INTSTS 0x24
177#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
178#define ICH6_REG_SYNC 0x34
179#define ICH6_REG_CORBLBASE 0x40
180#define ICH6_REG_CORBUBASE 0x44
181#define ICH6_REG_CORBWP 0x48
182#define ICH6_REG_CORBRP 0x4a
183#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
184#define ICH6_REG_CORBCTL 0x4c
185#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
186#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
187#define ICH6_REG_CORBSTS 0x4d
188#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
189#define ICH6_REG_CORBSIZE 0x4e
190
191#define ICH6_REG_RIRBLBASE 0x50
192#define ICH6_REG_RIRBUBASE 0x54
193#define ICH6_REG_RIRBWP 0x58
194#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
195#define ICH6_REG_RINTCNT 0x5a
196#define ICH6_REG_RIRBCTL 0x5c
197#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
198#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
199#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
200#define ICH6_REG_RIRBSTS 0x5d
201#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
202#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
203#define ICH6_REG_RIRBSIZE 0x5e
204
205#define ICH6_REG_IC 0x60
206#define ICH6_REG_IR 0x64
207#define ICH6_REG_IRS 0x68
208#define ICH6_IRS_VALID (1<<1)
209#define ICH6_IRS_BUSY (1<<0)
210
211#define ICH6_REG_DPLBASE 0x70
212#define ICH6_REG_DPUBASE 0x74
213#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
214
215/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
216enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
217
218/* stream register offsets from stream base */
219#define ICH6_REG_SD_CTL 0x00
220#define ICH6_REG_SD_STS 0x03
221#define ICH6_REG_SD_LPIB 0x04
222#define ICH6_REG_SD_CBL 0x08
223#define ICH6_REG_SD_LVI 0x0c
224#define ICH6_REG_SD_FIFOW 0x0e
225#define ICH6_REG_SD_FIFOSIZE 0x10
226#define ICH6_REG_SD_FORMAT 0x12
227#define ICH6_REG_SD_BDLPL 0x18
228#define ICH6_REG_SD_BDLPU 0x1c
229
230/* PCI space */
231#define ICH6_PCIREG_TCSEL 0x44
232
233/*
234 * other constants
235 */
236
237/* max number of SDs */
238/* ICH, ATI and VIA have 4 playback and 4 capture */
239#define ICH6_NUM_CAPTURE 4
240#define ICH6_NUM_PLAYBACK 4
241
242/* ULI has 6 playback and 5 capture */
243#define ULI_NUM_CAPTURE 5
244#define ULI_NUM_PLAYBACK 6
245
246/* ATI HDMI has 1 playback and 0 capture */
247#define ATIHDMI_NUM_CAPTURE 0
248#define ATIHDMI_NUM_PLAYBACK 1
249
250/* TERA has 4 playback and 3 capture */
251#define TERA_NUM_CAPTURE 3
252#define TERA_NUM_PLAYBACK 4
253
254/* this number is statically defined for simplicity */
255#define MAX_AZX_DEV 16
256
257/* max number of fragments - we may use more if allocating more pages for BDL */
258#define BDL_SIZE 4096
259#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
260#define AZX_MAX_FRAG 32
261/* max buffer size - no h/w limit, you can increase as you like */
262#define AZX_MAX_BUF_SIZE (1024*1024*1024)
263
264/* RIRB int mask: overrun[2], response[0] */
265#define RIRB_INT_RESPONSE 0x01
266#define RIRB_INT_OVERRUN 0x04
267#define RIRB_INT_MASK 0x05
268
269/* STATESTS int mask: S3,SD2,SD1,SD0 */
270#define AZX_MAX_CODECS 8
271#define AZX_DEFAULT_CODECS 4
272#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
273
274/* SD_CTL bits */
275#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
276#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
277#define SD_CTL_STRIPE (3 << 16) /* stripe control */
278#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
279#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
280#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
281#define SD_CTL_STREAM_TAG_SHIFT 20
282
283/* SD_CTL and SD_STS */
284#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
285#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
286#define SD_INT_COMPLETE 0x04 /* completion interrupt */
287#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
288 SD_INT_COMPLETE)
289
290/* SD_STS */
291#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
292
293/* INTCTL and INTSTS */
294#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
295#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
296#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
297
298/* below are so far hardcoded - should read registers in future */
299#define ICH6_MAX_CORB_ENTRIES 256
300#define ICH6_MAX_RIRB_ENTRIES 256
301
302/* position fix mode */
303enum {
304 POS_FIX_AUTO,
305 POS_FIX_LPIB,
306 POS_FIX_POSBUF,
307};
308
309/* Defines for ATI HD Audio support in SB450 south bridge */
310#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
311#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
312
313/* Defines for Nvidia HDA support */
314#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
315#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
316#define NVIDIA_HDA_ISTRM_COH 0x4d
317#define NVIDIA_HDA_OSTRM_COH 0x4c
318#define NVIDIA_HDA_ENABLE_COHBIT 0x01
319
320/* Defines for Intel SCH HDA snoop control */
321#define INTEL_SCH_HDA_DEVC 0x78
322#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
323
324/* Define IN stream 0 FIFO size offset in VIA controller */
325#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
326/* Define VIA HD Audio Device ID*/
327#define VIA_HDAC_DEVICE_ID 0x3288
328
329/* HD Audio class code */
330#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
331
332/*
333 */
334
335struct azx_dev {
336 struct snd_dma_buffer bdl; /* BDL buffer */
337 u32 *posbuf; /* position buffer pointer */
338
339 unsigned int bufsize; /* size of the play buffer in bytes */
340 unsigned int period_bytes; /* size of the period in bytes */
341 unsigned int frags; /* number for period in the play buffer */
342 unsigned int fifo_size; /* FIFO size */
343 unsigned long start_wallclk; /* start + minimum wallclk */
344 unsigned long period_wallclk; /* wallclk for period */
345
346 void __iomem *sd_addr; /* stream descriptor pointer */
347
348 u32 sd_int_sta_mask; /* stream int status mask */
349
350 /* pcm support */
351 struct snd_pcm_substream *substream; /* assigned substream,
352 * set in PCM open
353 */
354 unsigned int format_val; /* format value to be set in the
355 * controller and the codec
356 */
357 unsigned char stream_tag; /* assigned stream */
358 unsigned char index; /* stream index */
359 int device; /* last device number assigned to */
360
361 unsigned int opened :1;
362 unsigned int running :1;
363 unsigned int irq_pending :1;
364 /*
365 * For VIA:
366 * A flag to ensure DMA position is 0
367 * when link position is not greater than FIFO size
368 */
369 unsigned int insufficient :1;
370};
371
372/* CORB/RIRB */
373struct azx_rb {
374 u32 *buf; /* CORB/RIRB buffer
375 * Each CORB entry is 4byte, RIRB is 8byte
376 */
377 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
378 /* for RIRB */
379 unsigned short rp, wp; /* read/write pointers */
380 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
381 u32 res[AZX_MAX_CODECS]; /* last read value */
382};
383
384struct azx {
385 struct snd_card *card;
386 struct pci_dev *pci;
387 int dev_index;
388
389 /* chip type specific */
390 int driver_type;
391 int playback_streams;
392 int playback_index_offset;
393 int capture_streams;
394 int capture_index_offset;
395 int num_streams;
396
397 /* pci resources */
398 unsigned long addr;
399 void __iomem *remap_addr;
400 int irq;
401
402 /* locks */
403 spinlock_t reg_lock;
404 struct mutex open_mutex;
405
406 /* streams (x num_streams) */
407 struct azx_dev *azx_dev;
408
409 /* PCM */
410 struct snd_pcm *pcm[HDA_MAX_PCMS];
411
412 /* HD codec */
413 unsigned short codec_mask;
414 int codec_probe_mask; /* copied from probe_mask option */
415 struct hda_bus *bus;
416 unsigned int beep_mode;
417
418 /* CORB/RIRB */
419 struct azx_rb corb;
420 struct azx_rb rirb;
421
422 /* CORB/RIRB and position buffers */
423 struct snd_dma_buffer rb;
424 struct snd_dma_buffer posbuf;
425
426 /* flags */
427 int position_fix[2]; /* for both playback/capture streams */
428 int poll_count;
429 unsigned int running :1;
430 unsigned int initialized :1;
431 unsigned int single_cmd :1;
432 unsigned int polling_mode :1;
433 unsigned int msi :1;
434 unsigned int irq_pending_warned :1;
435 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
436 unsigned int probing :1; /* codec probing phase */
437
438 /* for debugging */
439 unsigned int last_cmd[AZX_MAX_CODECS];
440
441 /* for pending irqs */
442 struct work_struct irq_pending_work;
443
444 /* reboot notifier (for mysterious hangup problem at power-down) */
445 struct notifier_block reboot_notifier;
446};
447
448/* driver types */
449enum {
450 AZX_DRIVER_ICH,
451 AZX_DRIVER_PCH,
452 AZX_DRIVER_SCH,
453 AZX_DRIVER_ATI,
454 AZX_DRIVER_ATIHDMI,
455 AZX_DRIVER_VIA,
456 AZX_DRIVER_SIS,
457 AZX_DRIVER_ULI,
458 AZX_DRIVER_NVIDIA,
459 AZX_DRIVER_TERA,
460 AZX_DRIVER_GENERIC,
461 AZX_NUM_DRIVERS, /* keep this as last entry */
462};
463
464static char *driver_short_names[] __devinitdata = {
465 [AZX_DRIVER_ICH] = "HDA Intel",
466 [AZX_DRIVER_PCH] = "HDA Intel PCH",
467 [AZX_DRIVER_SCH] = "HDA Intel MID",
468 [AZX_DRIVER_ATI] = "HDA ATI SB",
469 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
470 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
471 [AZX_DRIVER_SIS] = "HDA SIS966",
472 [AZX_DRIVER_ULI] = "HDA ULI M5461",
473 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
474 [AZX_DRIVER_TERA] = "HDA Teradici",
475 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
476};
477
478/*
479 * macros for easy use
480 */
481#define azx_writel(chip,reg,value) \
482 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
483#define azx_readl(chip,reg) \
484 readl((chip)->remap_addr + ICH6_REG_##reg)
485#define azx_writew(chip,reg,value) \
486 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
487#define azx_readw(chip,reg) \
488 readw((chip)->remap_addr + ICH6_REG_##reg)
489#define azx_writeb(chip,reg,value) \
490 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
491#define azx_readb(chip,reg) \
492 readb((chip)->remap_addr + ICH6_REG_##reg)
493
494#define azx_sd_writel(dev,reg,value) \
495 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
496#define azx_sd_readl(dev,reg) \
497 readl((dev)->sd_addr + ICH6_REG_##reg)
498#define azx_sd_writew(dev,reg,value) \
499 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
500#define azx_sd_readw(dev,reg) \
501 readw((dev)->sd_addr + ICH6_REG_##reg)
502#define azx_sd_writeb(dev,reg,value) \
503 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
504#define azx_sd_readb(dev,reg) \
505 readb((dev)->sd_addr + ICH6_REG_##reg)
506
507/* for pcm support */
508#define get_azx_dev(substream) (substream->runtime->private_data)
509
510static int azx_acquire_irq(struct azx *chip, int do_disconnect);
511static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
512/*
513 * Interface for HD codec
514 */
515
516/*
517 * CORB / RIRB interface
518 */
519static int azx_alloc_cmd_io(struct azx *chip)
520{
521 int err;
522
523 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
524 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
525 snd_dma_pci_data(chip->pci),
526 PAGE_SIZE, &chip->rb);
527 if (err < 0) {
528 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
529 return err;
530 }
531 return 0;
532}
533
534static void azx_init_cmd_io(struct azx *chip)
535{
536 spin_lock_irq(&chip->reg_lock);
537 /* CORB set up */
538 chip->corb.addr = chip->rb.addr;
539 chip->corb.buf = (u32 *)chip->rb.area;
540 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
541 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
542
543 /* set the corb size to 256 entries (ULI requires explicitly) */
544 azx_writeb(chip, CORBSIZE, 0x02);
545 /* set the corb write pointer to 0 */
546 azx_writew(chip, CORBWP, 0);
547 /* reset the corb hw read pointer */
548 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
549 /* enable corb dma */
550 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
551
552 /* RIRB set up */
553 chip->rirb.addr = chip->rb.addr + 2048;
554 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
555 chip->rirb.wp = chip->rirb.rp = 0;
556 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
557 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
558 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
559
560 /* set the rirb size to 256 entries (ULI requires explicitly) */
561 azx_writeb(chip, RIRBSIZE, 0x02);
562 /* reset the rirb hw write pointer */
563 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
564 /* set N=1, get RIRB response interrupt for new entry */
565 azx_writew(chip, RINTCNT, 1);
566 /* enable rirb dma and response irq */
567 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
568 spin_unlock_irq(&chip->reg_lock);
569}
570
571static void azx_free_cmd_io(struct azx *chip)
572{
573 spin_lock_irq(&chip->reg_lock);
574 /* disable ringbuffer DMAs */
575 azx_writeb(chip, RIRBCTL, 0);
576 azx_writeb(chip, CORBCTL, 0);
577 spin_unlock_irq(&chip->reg_lock);
578}
579
580static unsigned int azx_command_addr(u32 cmd)
581{
582 unsigned int addr = cmd >> 28;
583
584 if (addr >= AZX_MAX_CODECS) {
585 snd_BUG();
586 addr = 0;
587 }
588
589 return addr;
590}
591
592static unsigned int azx_response_addr(u32 res)
593{
594 unsigned int addr = res & 0xf;
595
596 if (addr >= AZX_MAX_CODECS) {
597 snd_BUG();
598 addr = 0;
599 }
600
601 return addr;
602}
603
604/* send a command */
605static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
606{
607 struct azx *chip = bus->private_data;
608 unsigned int addr = azx_command_addr(val);
609 unsigned int wp;
610
611 spin_lock_irq(&chip->reg_lock);
612
613 /* add command to corb */
614 wp = azx_readb(chip, CORBWP);
615 wp++;
616 wp %= ICH6_MAX_CORB_ENTRIES;
617
618 chip->rirb.cmds[addr]++;
619 chip->corb.buf[wp] = cpu_to_le32(val);
620 azx_writel(chip, CORBWP, wp);
621
622 spin_unlock_irq(&chip->reg_lock);
623
624 return 0;
625}
626
627#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
628
629/* retrieve RIRB entry - called from interrupt handler */
630static void azx_update_rirb(struct azx *chip)
631{
632 unsigned int rp, wp;
633 unsigned int addr;
634 u32 res, res_ex;
635
636 wp = azx_readb(chip, RIRBWP);
637 if (wp == chip->rirb.wp)
638 return;
639 chip->rirb.wp = wp;
640
641 while (chip->rirb.rp != wp) {
642 chip->rirb.rp++;
643 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
644
645 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
646 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
647 res = le32_to_cpu(chip->rirb.buf[rp]);
648 addr = azx_response_addr(res_ex);
649 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
650 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
651 else if (chip->rirb.cmds[addr]) {
652 chip->rirb.res[addr] = res;
653 smp_wmb();
654 chip->rirb.cmds[addr]--;
655 } else
656 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
657 "last cmd=%#08x\n",
658 res, res_ex,
659 chip->last_cmd[addr]);
660 }
661}
662
663/* receive a response */
664static unsigned int azx_rirb_get_response(struct hda_bus *bus,
665 unsigned int addr)
666{
667 struct azx *chip = bus->private_data;
668 unsigned long timeout;
669 int do_poll = 0;
670
671 again:
672 timeout = jiffies + msecs_to_jiffies(1000);
673 for (;;) {
674 if (chip->polling_mode || do_poll) {
675 spin_lock_irq(&chip->reg_lock);
676 azx_update_rirb(chip);
677 spin_unlock_irq(&chip->reg_lock);
678 }
679 if (!chip->rirb.cmds[addr]) {
680 smp_rmb();
681 bus->rirb_error = 0;
682
683 if (!do_poll)
684 chip->poll_count = 0;
685 return chip->rirb.res[addr]; /* the last value */
686 }
687 if (time_after(jiffies, timeout))
688 break;
689 if (bus->needs_damn_long_delay)
690 msleep(2); /* temporary workaround */
691 else {
692 udelay(10);
693 cond_resched();
694 }
695 }
696
697 if (!chip->polling_mode && chip->poll_count < 2) {
698 snd_printdd(SFX "azx_get_response timeout, "
699 "polling the codec once: last cmd=0x%08x\n",
700 chip->last_cmd[addr]);
701 do_poll = 1;
702 chip->poll_count++;
703 goto again;
704 }
705
706
707 if (!chip->polling_mode) {
708 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
709 "switching to polling mode: last cmd=0x%08x\n",
710 chip->last_cmd[addr]);
711 chip->polling_mode = 1;
712 goto again;
713 }
714
715 if (chip->msi) {
716 snd_printk(KERN_WARNING SFX "No response from codec, "
717 "disabling MSI: last cmd=0x%08x\n",
718 chip->last_cmd[addr]);
719 free_irq(chip->irq, chip);
720 chip->irq = -1;
721 pci_disable_msi(chip->pci);
722 chip->msi = 0;
723 if (azx_acquire_irq(chip, 1) < 0) {
724 bus->rirb_error = 1;
725 return -1;
726 }
727 goto again;
728 }
729
730 if (chip->probing) {
731 /* If this critical timeout happens during the codec probing
732 * phase, this is likely an access to a non-existing codec
733 * slot. Better to return an error and reset the system.
734 */
735 return -1;
736 }
737
738 /* a fatal communication error; need either to reset or to fallback
739 * to the single_cmd mode
740 */
741 bus->rirb_error = 1;
742 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
743 bus->response_reset = 1;
744 return -1; /* give a chance to retry */
745 }
746
747 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
748 "switching to single_cmd mode: last cmd=0x%08x\n",
749 chip->last_cmd[addr]);
750 chip->single_cmd = 1;
751 bus->response_reset = 0;
752 /* release CORB/RIRB */
753 azx_free_cmd_io(chip);
754 /* disable unsolicited responses */
755 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
756 return -1;
757}
758
759/*
760 * Use the single immediate command instead of CORB/RIRB for simplicity
761 *
762 * Note: according to Intel, this is not preferred use. The command was
763 * intended for the BIOS only, and may get confused with unsolicited
764 * responses. So, we shouldn't use it for normal operation from the
765 * driver.
766 * I left the codes, however, for debugging/testing purposes.
767 */
768
769/* receive a response */
770static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
771{
772 int timeout = 50;
773
774 while (timeout--) {
775 /* check IRV busy bit */
776 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
777 /* reuse rirb.res as the response return value */
778 chip->rirb.res[addr] = azx_readl(chip, IR);
779 return 0;
780 }
781 udelay(1);
782 }
783 if (printk_ratelimit())
784 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
785 azx_readw(chip, IRS));
786 chip->rirb.res[addr] = -1;
787 return -EIO;
788}
789
790/* send a command */
791static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
792{
793 struct azx *chip = bus->private_data;
794 unsigned int addr = azx_command_addr(val);
795 int timeout = 50;
796
797 bus->rirb_error = 0;
798 while (timeout--) {
799 /* check ICB busy bit */
800 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
801 /* Clear IRV valid bit */
802 azx_writew(chip, IRS, azx_readw(chip, IRS) |
803 ICH6_IRS_VALID);
804 azx_writel(chip, IC, val);
805 azx_writew(chip, IRS, azx_readw(chip, IRS) |
806 ICH6_IRS_BUSY);
807 return azx_single_wait_for_response(chip, addr);
808 }
809 udelay(1);
810 }
811 if (printk_ratelimit())
812 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
813 azx_readw(chip, IRS), val);
814 return -EIO;
815}
816
817/* receive a response */
818static unsigned int azx_single_get_response(struct hda_bus *bus,
819 unsigned int addr)
820{
821 struct azx *chip = bus->private_data;
822 return chip->rirb.res[addr];
823}
824
825/*
826 * The below are the main callbacks from hda_codec.
827 *
828 * They are just the skeleton to call sub-callbacks according to the
829 * current setting of chip->single_cmd.
830 */
831
832/* send a command */
833static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
834{
835 struct azx *chip = bus->private_data;
836
837 chip->last_cmd[azx_command_addr(val)] = val;
838 if (chip->single_cmd)
839 return azx_single_send_cmd(bus, val);
840 else
841 return azx_corb_send_cmd(bus, val);
842}
843
844/* get a response */
845static unsigned int azx_get_response(struct hda_bus *bus,
846 unsigned int addr)
847{
848 struct azx *chip = bus->private_data;
849 if (chip->single_cmd)
850 return azx_single_get_response(bus, addr);
851 else
852 return azx_rirb_get_response(bus, addr);
853}
854
855#ifdef CONFIG_SND_HDA_POWER_SAVE
856static void azx_power_notify(struct hda_bus *bus);
857#endif
858
859/* reset codec link */
860static int azx_reset(struct azx *chip, int full_reset)
861{
862 int count;
863
864 if (!full_reset)
865 goto __skip;
866
867 /* clear STATESTS */
868 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
869
870 /* reset controller */
871 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
872
873 count = 50;
874 while (azx_readb(chip, GCTL) && --count)
875 msleep(1);
876
877 /* delay for >= 100us for codec PLL to settle per spec
878 * Rev 0.9 section 5.5.1
879 */
880 msleep(1);
881
882 /* Bring controller out of reset */
883 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
884
885 count = 50;
886 while (!azx_readb(chip, GCTL) && --count)
887 msleep(1);
888
889 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
890 msleep(1);
891
892 __skip:
893 /* check to see if controller is ready */
894 if (!azx_readb(chip, GCTL)) {
895 snd_printd(SFX "azx_reset: controller not ready!\n");
896 return -EBUSY;
897 }
898
899 /* Accept unsolicited responses */
900 if (!chip->single_cmd)
901 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
902 ICH6_GCTL_UNSOL);
903
904 /* detect codecs */
905 if (!chip->codec_mask) {
906 chip->codec_mask = azx_readw(chip, STATESTS);
907 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
908 }
909
910 return 0;
911}
912
913
914/*
915 * Lowlevel interface
916 */
917
918/* enable interrupts */
919static void azx_int_enable(struct azx *chip)
920{
921 /* enable controller CIE and GIE */
922 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
923 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
924}
925
926/* disable interrupts */
927static void azx_int_disable(struct azx *chip)
928{
929 int i;
930
931 /* disable interrupts in stream descriptor */
932 for (i = 0; i < chip->num_streams; i++) {
933 struct azx_dev *azx_dev = &chip->azx_dev[i];
934 azx_sd_writeb(azx_dev, SD_CTL,
935 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
936 }
937
938 /* disable SIE for all streams */
939 azx_writeb(chip, INTCTL, 0);
940
941 /* disable controller CIE and GIE */
942 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
943 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
944}
945
946/* clear interrupts */
947static void azx_int_clear(struct azx *chip)
948{
949 int i;
950
951 /* clear stream status */
952 for (i = 0; i < chip->num_streams; i++) {
953 struct azx_dev *azx_dev = &chip->azx_dev[i];
954 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
955 }
956
957 /* clear STATESTS */
958 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
959
960 /* clear rirb status */
961 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
962
963 /* clear int status */
964 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
965}
966
967/* start a stream */
968static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
969{
970 /*
971 * Before stream start, initialize parameter
972 */
973 azx_dev->insufficient = 1;
974
975 /* enable SIE */
976 azx_writel(chip, INTCTL,
977 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
978 /* set DMA start and interrupt mask */
979 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
980 SD_CTL_DMA_START | SD_INT_MASK);
981}
982
983/* stop DMA */
984static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
985{
986 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
987 ~(SD_CTL_DMA_START | SD_INT_MASK));
988 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
989}
990
991/* stop a stream */
992static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
993{
994 azx_stream_clear(chip, azx_dev);
995 /* disable SIE */
996 azx_writel(chip, INTCTL,
997 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
998}
999
1000
1001/*
1002 * reset and start the controller registers
1003 */
1004static void azx_init_chip(struct azx *chip, int full_reset)
1005{
1006 if (chip->initialized)
1007 return;
1008
1009 /* reset controller */
1010 azx_reset(chip, full_reset);
1011
1012 /* initialize interrupts */
1013 azx_int_clear(chip);
1014 azx_int_enable(chip);
1015
1016 /* initialize the codec command I/O */
1017 if (!chip->single_cmd)
1018 azx_init_cmd_io(chip);
1019
1020 /* program the position buffer */
1021 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1022 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1023
1024 chip->initialized = 1;
1025}
1026
1027/*
1028 * initialize the PCI registers
1029 */
1030/* update bits in a PCI register byte */
1031static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1032 unsigned char mask, unsigned char val)
1033{
1034 unsigned char data;
1035
1036 pci_read_config_byte(pci, reg, &data);
1037 data &= ~mask;
1038 data |= (val & mask);
1039 pci_write_config_byte(pci, reg, data);
1040}
1041
1042static void azx_init_pci(struct azx *chip)
1043{
1044 unsigned short snoop;
1045
1046 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1047 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1048 * Ensuring these bits are 0 clears playback static on some HD Audio
1049 * codecs
1050 */
1051 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1052
1053 switch (chip->driver_type) {
1054 case AZX_DRIVER_ATI:
1055 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1056 update_pci_byte(chip->pci,
1057 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1058 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1059 break;
1060 case AZX_DRIVER_NVIDIA:
1061 /* For NVIDIA HDA, enable snoop */
1062 update_pci_byte(chip->pci,
1063 NVIDIA_HDA_TRANSREG_ADDR,
1064 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1065 update_pci_byte(chip->pci,
1066 NVIDIA_HDA_ISTRM_COH,
1067 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1068 update_pci_byte(chip->pci,
1069 NVIDIA_HDA_OSTRM_COH,
1070 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1071 break;
1072 case AZX_DRIVER_SCH:
1073 case AZX_DRIVER_PCH:
1074 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1075 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1076 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1077 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1078 pci_read_config_word(chip->pci,
1079 INTEL_SCH_HDA_DEVC, &snoop);
1080 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1081 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1082 ? "Failed" : "OK");
1083 }
1084 break;
1085
1086 }
1087}
1088
1089
1090static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1091
1092/*
1093 * interrupt handler
1094 */
1095static irqreturn_t azx_interrupt(int irq, void *dev_id)
1096{
1097 struct azx *chip = dev_id;
1098 struct azx_dev *azx_dev;
1099 u32 status;
1100 u8 sd_status;
1101 int i, ok;
1102
1103 spin_lock(&chip->reg_lock);
1104
1105 status = azx_readl(chip, INTSTS);
1106 if (status == 0) {
1107 spin_unlock(&chip->reg_lock);
1108 return IRQ_NONE;
1109 }
1110
1111 for (i = 0; i < chip->num_streams; i++) {
1112 azx_dev = &chip->azx_dev[i];
1113 if (status & azx_dev->sd_int_sta_mask) {
1114 sd_status = azx_sd_readb(azx_dev, SD_STS);
1115 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1116 if (!azx_dev->substream || !azx_dev->running ||
1117 !(sd_status & SD_INT_COMPLETE))
1118 continue;
1119 /* check whether this IRQ is really acceptable */
1120 ok = azx_position_ok(chip, azx_dev);
1121 if (ok == 1) {
1122 azx_dev->irq_pending = 0;
1123 spin_unlock(&chip->reg_lock);
1124 snd_pcm_period_elapsed(azx_dev->substream);
1125 spin_lock(&chip->reg_lock);
1126 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1127 /* bogus IRQ, process it later */
1128 azx_dev->irq_pending = 1;
1129 queue_work(chip->bus->workq,
1130 &chip->irq_pending_work);
1131 }
1132 }
1133 }
1134
1135 /* clear rirb int */
1136 status = azx_readb(chip, RIRBSTS);
1137 if (status & RIRB_INT_MASK) {
1138 if (status & RIRB_INT_RESPONSE)
1139 azx_update_rirb(chip);
1140 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1141 }
1142
1143#if 0
1144 /* clear state status int */
1145 if (azx_readb(chip, STATESTS) & 0x04)
1146 azx_writeb(chip, STATESTS, 0x04);
1147#endif
1148 spin_unlock(&chip->reg_lock);
1149
1150 return IRQ_HANDLED;
1151}
1152
1153
1154/*
1155 * set up a BDL entry
1156 */
1157static int setup_bdle(struct snd_pcm_substream *substream,
1158 struct azx_dev *azx_dev, u32 **bdlp,
1159 int ofs, int size, int with_ioc)
1160{
1161 u32 *bdl = *bdlp;
1162
1163 while (size > 0) {
1164 dma_addr_t addr;
1165 int chunk;
1166
1167 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1168 return -EINVAL;
1169
1170 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1171 /* program the address field of the BDL entry */
1172 bdl[0] = cpu_to_le32((u32)addr);
1173 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1174 /* program the size field of the BDL entry */
1175 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1176 bdl[2] = cpu_to_le32(chunk);
1177 /* program the IOC to enable interrupt
1178 * only when the whole fragment is processed
1179 */
1180 size -= chunk;
1181 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1182 bdl += 4;
1183 azx_dev->frags++;
1184 ofs += chunk;
1185 }
1186 *bdlp = bdl;
1187 return ofs;
1188}
1189
1190/*
1191 * set up BDL entries
1192 */
1193static int azx_setup_periods(struct azx *chip,
1194 struct snd_pcm_substream *substream,
1195 struct azx_dev *azx_dev)
1196{
1197 u32 *bdl;
1198 int i, ofs, periods, period_bytes;
1199 int pos_adj;
1200
1201 /* reset BDL address */
1202 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1203 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1204
1205 period_bytes = azx_dev->period_bytes;
1206 periods = azx_dev->bufsize / period_bytes;
1207
1208 /* program the initial BDL entries */
1209 bdl = (u32 *)azx_dev->bdl.area;
1210 ofs = 0;
1211 azx_dev->frags = 0;
1212 pos_adj = bdl_pos_adj[chip->dev_index];
1213 if (pos_adj > 0) {
1214 struct snd_pcm_runtime *runtime = substream->runtime;
1215 int pos_align = pos_adj;
1216 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1217 if (!pos_adj)
1218 pos_adj = pos_align;
1219 else
1220 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1221 pos_align;
1222 pos_adj = frames_to_bytes(runtime, pos_adj);
1223 if (pos_adj >= period_bytes) {
1224 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1225 bdl_pos_adj[chip->dev_index]);
1226 pos_adj = 0;
1227 } else {
1228 ofs = setup_bdle(substream, azx_dev,
1229 &bdl, ofs, pos_adj, 1);
1230 if (ofs < 0)
1231 goto error;
1232 }
1233 } else
1234 pos_adj = 0;
1235 for (i = 0; i < periods; i++) {
1236 if (i == periods - 1 && pos_adj)
1237 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1238 period_bytes - pos_adj, 0);
1239 else
1240 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1241 period_bytes, 1);
1242 if (ofs < 0)
1243 goto error;
1244 }
1245 return 0;
1246
1247 error:
1248 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1249 azx_dev->bufsize, period_bytes);
1250 return -EINVAL;
1251}
1252
1253/* reset stream */
1254static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1255{
1256 unsigned char val;
1257 int timeout;
1258
1259 azx_stream_clear(chip, azx_dev);
1260
1261 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1262 SD_CTL_STREAM_RESET);
1263 udelay(3);
1264 timeout = 300;
1265 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1266 --timeout)
1267 ;
1268 val &= ~SD_CTL_STREAM_RESET;
1269 azx_sd_writeb(azx_dev, SD_CTL, val);
1270 udelay(3);
1271
1272 timeout = 300;
1273 /* waiting for hardware to report that the stream is out of reset */
1274 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1275 --timeout)
1276 ;
1277
1278 /* reset first position - may not be synced with hw at this time */
1279 *azx_dev->posbuf = 0;
1280}
1281
1282/*
1283 * set up the SD for streaming
1284 */
1285static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1286{
1287 /* make sure the run bit is zero for SD */
1288 azx_stream_clear(chip, azx_dev);
1289 /* program the stream_tag */
1290 azx_sd_writel(azx_dev, SD_CTL,
1291 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1292 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1293
1294 /* program the length of samples in cyclic buffer */
1295 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1296
1297 /* program the stream format */
1298 /* this value needs to be the same as the one programmed */
1299 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1300
1301 /* program the stream LVI (last valid index) of the BDL */
1302 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1303
1304 /* program the BDL address */
1305 /* lower BDL address */
1306 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1307 /* upper BDL address */
1308 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1309
1310 /* enable the position buffer */
1311 if (chip->position_fix[0] == POS_FIX_POSBUF ||
1312 chip->position_fix[0] == POS_FIX_AUTO ||
1313 chip->position_fix[1] == POS_FIX_POSBUF ||
1314 chip->position_fix[1] == POS_FIX_AUTO ||
1315 chip->via_dmapos_patch) {
1316 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1317 azx_writel(chip, DPLBASE,
1318 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1319 }
1320
1321 /* set the interrupt enable bits in the descriptor control register */
1322 azx_sd_writel(azx_dev, SD_CTL,
1323 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1324
1325 return 0;
1326}
1327
1328/*
1329 * Probe the given codec address
1330 */
1331static int probe_codec(struct azx *chip, int addr)
1332{
1333 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1334 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1335 unsigned int res;
1336
1337 mutex_lock(&chip->bus->cmd_mutex);
1338 chip->probing = 1;
1339 azx_send_cmd(chip->bus, cmd);
1340 res = azx_get_response(chip->bus, addr);
1341 chip->probing = 0;
1342 mutex_unlock(&chip->bus->cmd_mutex);
1343 if (res == -1)
1344 return -EIO;
1345 snd_printdd(SFX "codec #%d probed OK\n", addr);
1346 return 0;
1347}
1348
1349static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1350 struct hda_pcm *cpcm);
1351static void azx_stop_chip(struct azx *chip);
1352
1353static void azx_bus_reset(struct hda_bus *bus)
1354{
1355 struct azx *chip = bus->private_data;
1356
1357 bus->in_reset = 1;
1358 azx_stop_chip(chip);
1359 azx_init_chip(chip, 1);
1360#ifdef CONFIG_PM
1361 if (chip->initialized) {
1362 int i;
1363
1364 for (i = 0; i < HDA_MAX_PCMS; i++)
1365 snd_pcm_suspend_all(chip->pcm[i]);
1366 snd_hda_suspend(chip->bus);
1367 snd_hda_resume(chip->bus);
1368 }
1369#endif
1370 bus->in_reset = 0;
1371}
1372
1373/*
1374 * Codec initialization
1375 */
1376
1377/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1378static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1379 [AZX_DRIVER_NVIDIA] = 8,
1380 [AZX_DRIVER_TERA] = 1,
1381};
1382
1383static int __devinit azx_codec_create(struct azx *chip, const char *model)
1384{
1385 struct hda_bus_template bus_temp;
1386 int c, codecs, err;
1387 int max_slots;
1388
1389 memset(&bus_temp, 0, sizeof(bus_temp));
1390 bus_temp.private_data = chip;
1391 bus_temp.modelname = model;
1392 bus_temp.pci = chip->pci;
1393 bus_temp.ops.command = azx_send_cmd;
1394 bus_temp.ops.get_response = azx_get_response;
1395 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1396 bus_temp.ops.bus_reset = azx_bus_reset;
1397#ifdef CONFIG_SND_HDA_POWER_SAVE
1398 bus_temp.power_save = &power_save;
1399 bus_temp.ops.pm_notify = azx_power_notify;
1400#endif
1401
1402 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1403 if (err < 0)
1404 return err;
1405
1406 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1407 chip->bus->needs_damn_long_delay = 1;
1408
1409 codecs = 0;
1410 max_slots = azx_max_codecs[chip->driver_type];
1411 if (!max_slots)
1412 max_slots = AZX_DEFAULT_CODECS;
1413
1414 /* First try to probe all given codec slots */
1415 for (c = 0; c < max_slots; c++) {
1416 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1417 if (probe_codec(chip, c) < 0) {
1418 /* Some BIOSen give you wrong codec addresses
1419 * that don't exist
1420 */
1421 snd_printk(KERN_WARNING SFX
1422 "Codec #%d probe error; "
1423 "disabling it...\n", c);
1424 chip->codec_mask &= ~(1 << c);
1425 /* More badly, accessing to a non-existing
1426 * codec often screws up the controller chip,
1427 * and disturbs the further communications.
1428 * Thus if an error occurs during probing,
1429 * better to reset the controller chip to
1430 * get back to the sanity state.
1431 */
1432 azx_stop_chip(chip);
1433 azx_init_chip(chip, 1);
1434 }
1435 }
1436 }
1437
1438 /* Then create codec instances */
1439 for (c = 0; c < max_slots; c++) {
1440 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1441 struct hda_codec *codec;
1442 err = snd_hda_codec_new(chip->bus, c, &codec);
1443 if (err < 0)
1444 continue;
1445 codec->beep_mode = chip->beep_mode;
1446 codecs++;
1447 }
1448 }
1449 if (!codecs) {
1450 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1451 return -ENXIO;
1452 }
1453 return 0;
1454}
1455
1456/* configure each codec instance */
1457static int __devinit azx_codec_configure(struct azx *chip)
1458{
1459 struct hda_codec *codec;
1460 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1461 snd_hda_codec_configure(codec);
1462 }
1463 return 0;
1464}
1465
1466
1467/*
1468 * PCM support
1469 */
1470
1471/* assign a stream for the PCM */
1472static inline struct azx_dev *
1473azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1474{
1475 int dev, i, nums;
1476 struct azx_dev *res = NULL;
1477
1478 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1479 dev = chip->playback_index_offset;
1480 nums = chip->playback_streams;
1481 } else {
1482 dev = chip->capture_index_offset;
1483 nums = chip->capture_streams;
1484 }
1485 for (i = 0; i < nums; i++, dev++)
1486 if (!chip->azx_dev[dev].opened) {
1487 res = &chip->azx_dev[dev];
1488 if (res->device == substream->pcm->device)
1489 break;
1490 }
1491 if (res) {
1492 res->opened = 1;
1493 res->device = substream->pcm->device;
1494 }
1495 return res;
1496}
1497
1498/* release the assigned stream */
1499static inline void azx_release_device(struct azx_dev *azx_dev)
1500{
1501 azx_dev->opened = 0;
1502}
1503
1504static struct snd_pcm_hardware azx_pcm_hw = {
1505 .info = (SNDRV_PCM_INFO_MMAP |
1506 SNDRV_PCM_INFO_INTERLEAVED |
1507 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1508 SNDRV_PCM_INFO_MMAP_VALID |
1509 /* No full-resume yet implemented */
1510 /* SNDRV_PCM_INFO_RESUME |*/
1511 SNDRV_PCM_INFO_PAUSE |
1512 SNDRV_PCM_INFO_SYNC_START),
1513 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1514 .rates = SNDRV_PCM_RATE_48000,
1515 .rate_min = 48000,
1516 .rate_max = 48000,
1517 .channels_min = 2,
1518 .channels_max = 2,
1519 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1520 .period_bytes_min = 128,
1521 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1522 .periods_min = 2,
1523 .periods_max = AZX_MAX_FRAG,
1524 .fifo_size = 0,
1525};
1526
1527struct azx_pcm {
1528 struct azx *chip;
1529 struct hda_codec *codec;
1530 struct hda_pcm_stream *hinfo[2];
1531};
1532
1533static int azx_pcm_open(struct snd_pcm_substream *substream)
1534{
1535 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1536 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1537 struct azx *chip = apcm->chip;
1538 struct azx_dev *azx_dev;
1539 struct snd_pcm_runtime *runtime = substream->runtime;
1540 unsigned long flags;
1541 int err;
1542
1543 mutex_lock(&chip->open_mutex);
1544 azx_dev = azx_assign_device(chip, substream);
1545 if (azx_dev == NULL) {
1546 mutex_unlock(&chip->open_mutex);
1547 return -EBUSY;
1548 }
1549 runtime->hw = azx_pcm_hw;
1550 runtime->hw.channels_min = hinfo->channels_min;
1551 runtime->hw.channels_max = hinfo->channels_max;
1552 runtime->hw.formats = hinfo->formats;
1553 runtime->hw.rates = hinfo->rates;
1554 snd_pcm_limit_hw_rates(runtime);
1555 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1556 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1557 128);
1558 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1559 128);
1560 snd_hda_power_up(apcm->codec);
1561 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1562 if (err < 0) {
1563 azx_release_device(azx_dev);
1564 snd_hda_power_down(apcm->codec);
1565 mutex_unlock(&chip->open_mutex);
1566 return err;
1567 }
1568 snd_pcm_limit_hw_rates(runtime);
1569 /* sanity check */
1570 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1571 snd_BUG_ON(!runtime->hw.channels_max) ||
1572 snd_BUG_ON(!runtime->hw.formats) ||
1573 snd_BUG_ON(!runtime->hw.rates)) {
1574 azx_release_device(azx_dev);
1575 hinfo->ops.close(hinfo, apcm->codec, substream);
1576 snd_hda_power_down(apcm->codec);
1577 mutex_unlock(&chip->open_mutex);
1578 return -EINVAL;
1579 }
1580 spin_lock_irqsave(&chip->reg_lock, flags);
1581 azx_dev->substream = substream;
1582 azx_dev->running = 0;
1583 spin_unlock_irqrestore(&chip->reg_lock, flags);
1584
1585 runtime->private_data = azx_dev;
1586 snd_pcm_set_sync(substream);
1587 mutex_unlock(&chip->open_mutex);
1588 return 0;
1589}
1590
1591static int azx_pcm_close(struct snd_pcm_substream *substream)
1592{
1593 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1594 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1595 struct azx *chip = apcm->chip;
1596 struct azx_dev *azx_dev = get_azx_dev(substream);
1597 unsigned long flags;
1598
1599 mutex_lock(&chip->open_mutex);
1600 spin_lock_irqsave(&chip->reg_lock, flags);
1601 azx_dev->substream = NULL;
1602 azx_dev->running = 0;
1603 spin_unlock_irqrestore(&chip->reg_lock, flags);
1604 azx_release_device(azx_dev);
1605 hinfo->ops.close(hinfo, apcm->codec, substream);
1606 snd_hda_power_down(apcm->codec);
1607 mutex_unlock(&chip->open_mutex);
1608 return 0;
1609}
1610
1611static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1612 struct snd_pcm_hw_params *hw_params)
1613{
1614 struct azx_dev *azx_dev = get_azx_dev(substream);
1615
1616 azx_dev->bufsize = 0;
1617 azx_dev->period_bytes = 0;
1618 azx_dev->format_val = 0;
1619 return snd_pcm_lib_malloc_pages(substream,
1620 params_buffer_bytes(hw_params));
1621}
1622
1623static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1624{
1625 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1626 struct azx_dev *azx_dev = get_azx_dev(substream);
1627 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1628
1629 /* reset BDL address */
1630 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1631 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1632 azx_sd_writel(azx_dev, SD_CTL, 0);
1633 azx_dev->bufsize = 0;
1634 azx_dev->period_bytes = 0;
1635 azx_dev->format_val = 0;
1636
1637 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1638
1639 return snd_pcm_lib_free_pages(substream);
1640}
1641
1642static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1643{
1644 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1645 struct azx *chip = apcm->chip;
1646 struct azx_dev *azx_dev = get_azx_dev(substream);
1647 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1648 struct snd_pcm_runtime *runtime = substream->runtime;
1649 unsigned int bufsize, period_bytes, format_val;
1650 int err;
1651
1652 azx_stream_reset(chip, azx_dev);
1653 format_val = snd_hda_calc_stream_format(runtime->rate,
1654 runtime->channels,
1655 runtime->format,
1656 hinfo->maxbps);
1657 if (!format_val) {
1658 snd_printk(KERN_ERR SFX
1659 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1660 runtime->rate, runtime->channels, runtime->format);
1661 return -EINVAL;
1662 }
1663
1664 bufsize = snd_pcm_lib_buffer_bytes(substream);
1665 period_bytes = snd_pcm_lib_period_bytes(substream);
1666
1667 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1668 bufsize, format_val);
1669
1670 if (bufsize != azx_dev->bufsize ||
1671 period_bytes != azx_dev->period_bytes ||
1672 format_val != azx_dev->format_val) {
1673 azx_dev->bufsize = bufsize;
1674 azx_dev->period_bytes = period_bytes;
1675 azx_dev->format_val = format_val;
1676 err = azx_setup_periods(chip, substream, azx_dev);
1677 if (err < 0)
1678 return err;
1679 }
1680
1681 /* wallclk has 24Mhz clock source */
1682 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1683 runtime->rate) * 1000);
1684 azx_setup_controller(chip, azx_dev);
1685 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1686 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1687 else
1688 azx_dev->fifo_size = 0;
1689
1690 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1691 azx_dev->format_val, substream);
1692}
1693
1694static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1695{
1696 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1697 struct azx *chip = apcm->chip;
1698 struct azx_dev *azx_dev;
1699 struct snd_pcm_substream *s;
1700 int rstart = 0, start, nsync = 0, sbits = 0;
1701 int nwait, timeout;
1702
1703 switch (cmd) {
1704 case SNDRV_PCM_TRIGGER_START:
1705 rstart = 1;
1706 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1707 case SNDRV_PCM_TRIGGER_RESUME:
1708 start = 1;
1709 break;
1710 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1711 case SNDRV_PCM_TRIGGER_SUSPEND:
1712 case SNDRV_PCM_TRIGGER_STOP:
1713 start = 0;
1714 break;
1715 default:
1716 return -EINVAL;
1717 }
1718
1719 snd_pcm_group_for_each_entry(s, substream) {
1720 if (s->pcm->card != substream->pcm->card)
1721 continue;
1722 azx_dev = get_azx_dev(s);
1723 sbits |= 1 << azx_dev->index;
1724 nsync++;
1725 snd_pcm_trigger_done(s, substream);
1726 }
1727
1728 spin_lock(&chip->reg_lock);
1729 if (nsync > 1) {
1730 /* first, set SYNC bits of corresponding streams */
1731 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1732 }
1733 snd_pcm_group_for_each_entry(s, substream) {
1734 if (s->pcm->card != substream->pcm->card)
1735 continue;
1736 azx_dev = get_azx_dev(s);
1737 if (start) {
1738 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1739 if (!rstart)
1740 azx_dev->start_wallclk -=
1741 azx_dev->period_wallclk;
1742 azx_stream_start(chip, azx_dev);
1743 } else {
1744 azx_stream_stop(chip, azx_dev);
1745 }
1746 azx_dev->running = start;
1747 }
1748 spin_unlock(&chip->reg_lock);
1749 if (start) {
1750 if (nsync == 1)
1751 return 0;
1752 /* wait until all FIFOs get ready */
1753 for (timeout = 5000; timeout; timeout--) {
1754 nwait = 0;
1755 snd_pcm_group_for_each_entry(s, substream) {
1756 if (s->pcm->card != substream->pcm->card)
1757 continue;
1758 azx_dev = get_azx_dev(s);
1759 if (!(azx_sd_readb(azx_dev, SD_STS) &
1760 SD_STS_FIFO_READY))
1761 nwait++;
1762 }
1763 if (!nwait)
1764 break;
1765 cpu_relax();
1766 }
1767 } else {
1768 /* wait until all RUN bits are cleared */
1769 for (timeout = 5000; timeout; timeout--) {
1770 nwait = 0;
1771 snd_pcm_group_for_each_entry(s, substream) {
1772 if (s->pcm->card != substream->pcm->card)
1773 continue;
1774 azx_dev = get_azx_dev(s);
1775 if (azx_sd_readb(azx_dev, SD_CTL) &
1776 SD_CTL_DMA_START)
1777 nwait++;
1778 }
1779 if (!nwait)
1780 break;
1781 cpu_relax();
1782 }
1783 }
1784 if (nsync > 1) {
1785 spin_lock(&chip->reg_lock);
1786 /* reset SYNC bits */
1787 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1788 spin_unlock(&chip->reg_lock);
1789 }
1790 return 0;
1791}
1792
1793/* get the current DMA position with correction on VIA chips */
1794static unsigned int azx_via_get_position(struct azx *chip,
1795 struct azx_dev *azx_dev)
1796{
1797 unsigned int link_pos, mini_pos, bound_pos;
1798 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1799 unsigned int fifo_size;
1800
1801 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1802 if (azx_dev->index >= 4) {
1803 /* Playback, no problem using link position */
1804 return link_pos;
1805 }
1806
1807 /* Capture */
1808 /* For new chipset,
1809 * use mod to get the DMA position just like old chipset
1810 */
1811 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1812 mod_dma_pos %= azx_dev->period_bytes;
1813
1814 /* azx_dev->fifo_size can't get FIFO size of in stream.
1815 * Get from base address + offset.
1816 */
1817 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1818
1819 if (azx_dev->insufficient) {
1820 /* Link position never gather than FIFO size */
1821 if (link_pos <= fifo_size)
1822 return 0;
1823
1824 azx_dev->insufficient = 0;
1825 }
1826
1827 if (link_pos <= fifo_size)
1828 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1829 else
1830 mini_pos = link_pos - fifo_size;
1831
1832 /* Find nearest previous boudary */
1833 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1834 mod_link_pos = link_pos % azx_dev->period_bytes;
1835 if (mod_link_pos >= fifo_size)
1836 bound_pos = link_pos - mod_link_pos;
1837 else if (mod_dma_pos >= mod_mini_pos)
1838 bound_pos = mini_pos - mod_mini_pos;
1839 else {
1840 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1841 if (bound_pos >= azx_dev->bufsize)
1842 bound_pos = 0;
1843 }
1844
1845 /* Calculate real DMA position we want */
1846 return bound_pos + mod_dma_pos;
1847}
1848
1849static unsigned int azx_get_position(struct azx *chip,
1850 struct azx_dev *azx_dev)
1851{
1852 unsigned int pos;
1853
1854 if (chip->via_dmapos_patch)
1855 pos = azx_via_get_position(chip, azx_dev);
1856 else {
1857 int stream = azx_dev->substream->stream;
1858 if (chip->position_fix[stream] == POS_FIX_POSBUF ||
1859 chip->position_fix[stream] == POS_FIX_AUTO) {
1860 /* use the position buffer */
1861 pos = le32_to_cpu(*azx_dev->posbuf);
1862 } else {
1863 /* read LPIB */
1864 pos = azx_sd_readl(azx_dev, SD_LPIB);
1865 }
1866 }
1867 if (pos >= azx_dev->bufsize)
1868 pos = 0;
1869 return pos;
1870}
1871
1872static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1873{
1874 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1875 struct azx *chip = apcm->chip;
1876 struct azx_dev *azx_dev = get_azx_dev(substream);
1877 return bytes_to_frames(substream->runtime,
1878 azx_get_position(chip, azx_dev));
1879}
1880
1881/*
1882 * Check whether the current DMA position is acceptable for updating
1883 * periods. Returns non-zero if it's OK.
1884 *
1885 * Many HD-audio controllers appear pretty inaccurate about
1886 * the update-IRQ timing. The IRQ is issued before actually the
1887 * data is processed. So, we need to process it afterwords in a
1888 * workqueue.
1889 */
1890static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1891{
1892 u32 wallclk;
1893 unsigned int pos;
1894 int stream;
1895
1896 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1897 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1898 return -1; /* bogus (too early) interrupt */
1899
1900 stream = azx_dev->substream->stream;
1901 pos = azx_get_position(chip, azx_dev);
1902 if (chip->position_fix[stream] == POS_FIX_AUTO) {
1903 if (!pos) {
1904 printk(KERN_WARNING
1905 "hda-intel: Invalid position buffer, "
1906 "using LPIB read method instead.\n");
1907 chip->position_fix[stream] = POS_FIX_LPIB;
1908 pos = azx_get_position(chip, azx_dev);
1909 } else
1910 chip->position_fix[stream] = POS_FIX_POSBUF;
1911 }
1912
1913 if (WARN_ONCE(!azx_dev->period_bytes,
1914 "hda-intel: zero azx_dev->period_bytes"))
1915 return -1; /* this shouldn't happen! */
1916 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1917 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1918 /* NG - it's below the first next period boundary */
1919 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
1920 azx_dev->start_wallclk += wallclk;
1921 return 1; /* OK, it's fine */
1922}
1923
1924/*
1925 * The work for pending PCM period updates.
1926 */
1927static void azx_irq_pending_work(struct work_struct *work)
1928{
1929 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1930 int i, pending, ok;
1931
1932 if (!chip->irq_pending_warned) {
1933 printk(KERN_WARNING
1934 "hda-intel: IRQ timing workaround is activated "
1935 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1936 chip->card->number);
1937 chip->irq_pending_warned = 1;
1938 }
1939
1940 for (;;) {
1941 pending = 0;
1942 spin_lock_irq(&chip->reg_lock);
1943 for (i = 0; i < chip->num_streams; i++) {
1944 struct azx_dev *azx_dev = &chip->azx_dev[i];
1945 if (!azx_dev->irq_pending ||
1946 !azx_dev->substream ||
1947 !azx_dev->running)
1948 continue;
1949 ok = azx_position_ok(chip, azx_dev);
1950 if (ok > 0) {
1951 azx_dev->irq_pending = 0;
1952 spin_unlock(&chip->reg_lock);
1953 snd_pcm_period_elapsed(azx_dev->substream);
1954 spin_lock(&chip->reg_lock);
1955 } else if (ok < 0) {
1956 pending = 0; /* too early */
1957 } else
1958 pending++;
1959 }
1960 spin_unlock_irq(&chip->reg_lock);
1961 if (!pending)
1962 return;
1963 cond_resched();
1964 }
1965}
1966
1967/* clear irq_pending flags and assure no on-going workq */
1968static void azx_clear_irq_pending(struct azx *chip)
1969{
1970 int i;
1971
1972 spin_lock_irq(&chip->reg_lock);
1973 for (i = 0; i < chip->num_streams; i++)
1974 chip->azx_dev[i].irq_pending = 0;
1975 spin_unlock_irq(&chip->reg_lock);
1976}
1977
1978static struct snd_pcm_ops azx_pcm_ops = {
1979 .open = azx_pcm_open,
1980 .close = azx_pcm_close,
1981 .ioctl = snd_pcm_lib_ioctl,
1982 .hw_params = azx_pcm_hw_params,
1983 .hw_free = azx_pcm_hw_free,
1984 .prepare = azx_pcm_prepare,
1985 .trigger = azx_pcm_trigger,
1986 .pointer = azx_pcm_pointer,
1987 .page = snd_pcm_sgbuf_ops_page,
1988};
1989
1990static void azx_pcm_free(struct snd_pcm *pcm)
1991{
1992 struct azx_pcm *apcm = pcm->private_data;
1993 if (apcm) {
1994 apcm->chip->pcm[pcm->device] = NULL;
1995 kfree(apcm);
1996 }
1997}
1998
1999static int
2000azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2001 struct hda_pcm *cpcm)
2002{
2003 struct azx *chip = bus->private_data;
2004 struct snd_pcm *pcm;
2005 struct azx_pcm *apcm;
2006 int pcm_dev = cpcm->device;
2007 int s, err;
2008 size_t prealloc_min = 64*1024; /* 64KB */
2009
2010 if (pcm_dev >= HDA_MAX_PCMS) {
2011 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2012 pcm_dev);
2013 return -EINVAL;
2014 }
2015 if (chip->pcm[pcm_dev]) {
2016 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2017 return -EBUSY;
2018 }
2019 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2020 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2021 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2022 &pcm);
2023 if (err < 0)
2024 return err;
2025 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2026 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2027 if (apcm == NULL)
2028 return -ENOMEM;
2029 apcm->chip = chip;
2030 apcm->codec = codec;
2031 pcm->private_data = apcm;
2032 pcm->private_free = azx_pcm_free;
2033 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2034 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2035 chip->pcm[pcm_dev] = pcm;
2036 cpcm->pcm = pcm;
2037 for (s = 0; s < 2; s++) {
2038 apcm->hinfo[s] = &cpcm->stream[s];
2039 if (cpcm->stream[s].substreams)
2040 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2041 }
2042
2043 /* buffer pre-allocation */
2044
2045 /* subtle, don't allocate a big buffer for modems...
2046 * also, don't just test 32BIT_MASK, since azx supports
2047 * 64-bit DMA in some cases.
2048 */
2049 /* lennart wants a 2.2MB buffer for 2sec of 48khz */
2050 if (pcm->dev_class == SNDRV_PCM_CLASS_GENERIC &&
2051 chip->pci->dma_mask >= DMA_32BIT_MASK)
2052 prealloc_min = 4 * 1024 * 1024; /* 4MB */
2053
2054 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2055 snd_dma_pci_data(chip->pci),
2056 prealloc_min, 32 * 1024 * 1024);
2057 return 0;
2058}
2059
2060/*
2061 * mixer creation - all stuff is implemented in hda module
2062 */
2063static int __devinit azx_mixer_create(struct azx *chip)
2064{
2065 return snd_hda_build_controls(chip->bus);
2066}
2067
2068
2069/*
2070 * initialize SD streams
2071 */
2072static int __devinit azx_init_stream(struct azx *chip)
2073{
2074 int i;
2075
2076 /* initialize each stream (aka device)
2077 * assign the starting bdl address to each stream (device)
2078 * and initialize
2079 */
2080 for (i = 0; i < chip->num_streams; i++) {
2081 struct azx_dev *azx_dev = &chip->azx_dev[i];
2082 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2083 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2084 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2085 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2086 azx_dev->sd_int_sta_mask = 1 << i;
2087 /* stream tag: must be non-zero and unique */
2088 azx_dev->index = i;
2089 azx_dev->stream_tag = i + 1;
2090 }
2091
2092 return 0;
2093}
2094
2095static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2096{
2097 if (request_irq(chip->pci->irq, azx_interrupt,
2098 chip->msi ? 0 : IRQF_SHARED,
2099 "hda_intel", chip)) {
2100 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2101 "disabling device\n", chip->pci->irq);
2102 if (do_disconnect)
2103 snd_card_disconnect(chip->card);
2104 return -1;
2105 }
2106 chip->irq = chip->pci->irq;
2107 pci_intx(chip->pci, !chip->msi);
2108 return 0;
2109}
2110
2111
2112static void azx_stop_chip(struct azx *chip)
2113{
2114 if (!chip->initialized)
2115 return;
2116
2117 /* disable interrupts */
2118 azx_int_disable(chip);
2119 azx_int_clear(chip);
2120
2121 /* disable CORB/RIRB */
2122 azx_free_cmd_io(chip);
2123
2124 /* disable position buffer */
2125 azx_writel(chip, DPLBASE, 0);
2126 azx_writel(chip, DPUBASE, 0);
2127
2128 chip->initialized = 0;
2129}
2130
2131#ifdef CONFIG_SND_HDA_POWER_SAVE
2132/* power-up/down the controller */
2133static void azx_power_notify(struct hda_bus *bus)
2134{
2135 struct azx *chip = bus->private_data;
2136 struct hda_codec *c;
2137 int power_on = 0;
2138
2139 list_for_each_entry(c, &bus->codec_list, list) {
2140 if (c->power_on) {
2141 power_on = 1;
2142 break;
2143 }
2144 }
2145 if (power_on)
2146 azx_init_chip(chip, 1);
2147 else if (chip->running && power_save_controller &&
2148 !bus->power_keep_link_on)
2149 azx_stop_chip(chip);
2150}
2151#endif /* CONFIG_SND_HDA_POWER_SAVE */
2152
2153#ifdef CONFIG_PM
2154/*
2155 * power management
2156 */
2157
2158static int snd_hda_codecs_inuse(struct hda_bus *bus)
2159{
2160 struct hda_codec *codec;
2161
2162 list_for_each_entry(codec, &bus->codec_list, list) {
2163 if (snd_hda_codec_needs_resume(codec))
2164 return 1;
2165 }
2166 return 0;
2167}
2168
2169static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2170{
2171 struct snd_card *card = pci_get_drvdata(pci);
2172 struct azx *chip = card->private_data;
2173 int i;
2174
2175 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2176 azx_clear_irq_pending(chip);
2177 for (i = 0; i < HDA_MAX_PCMS; i++)
2178 snd_pcm_suspend_all(chip->pcm[i]);
2179 if (chip->initialized)
2180 snd_hda_suspend(chip->bus);
2181 azx_stop_chip(chip);
2182 if (chip->irq >= 0) {
2183 free_irq(chip->irq, chip);
2184 chip->irq = -1;
2185 }
2186 if (chip->msi)
2187 pci_disable_msi(chip->pci);
2188 pci_disable_device(pci);
2189 pci_save_state(pci);
2190 pci_set_power_state(pci, pci_choose_state(pci, state));
2191 return 0;
2192}
2193
2194static int azx_resume(struct pci_dev *pci)
2195{
2196 struct snd_card *card = pci_get_drvdata(pci);
2197 struct azx *chip = card->private_data;
2198
2199 pci_set_power_state(pci, PCI_D0);
2200 pci_restore_state(pci);
2201 if (pci_enable_device(pci) < 0) {
2202 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2203 "disabling device\n");
2204 snd_card_disconnect(card);
2205 return -EIO;
2206 }
2207 pci_set_master(pci);
2208 if (chip->msi)
2209 if (pci_enable_msi(pci) < 0)
2210 chip->msi = 0;
2211 if (azx_acquire_irq(chip, 1) < 0)
2212 return -EIO;
2213 azx_init_pci(chip);
2214
2215 if (snd_hda_codecs_inuse(chip->bus))
2216 azx_init_chip(chip, 1);
2217
2218 snd_hda_resume(chip->bus);
2219 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2220 return 0;
2221}
2222#endif /* CONFIG_PM */
2223
2224
2225/*
2226 * reboot notifier for hang-up problem at power-down
2227 */
2228static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2229{
2230 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2231 snd_hda_bus_reboot_notify(chip->bus);
2232 azx_stop_chip(chip);
2233 return NOTIFY_OK;
2234}
2235
2236static void azx_notifier_register(struct azx *chip)
2237{
2238 chip->reboot_notifier.notifier_call = azx_halt;
2239 register_reboot_notifier(&chip->reboot_notifier);
2240}
2241
2242static void azx_notifier_unregister(struct azx *chip)
2243{
2244 if (chip->reboot_notifier.notifier_call)
2245 unregister_reboot_notifier(&chip->reboot_notifier);
2246}
2247
2248/*
2249 * destructor
2250 */
2251static int azx_free(struct azx *chip)
2252{
2253 int i;
2254
2255 azx_notifier_unregister(chip);
2256
2257 if (chip->initialized) {
2258 azx_clear_irq_pending(chip);
2259 for (i = 0; i < chip->num_streams; i++)
2260 azx_stream_stop(chip, &chip->azx_dev[i]);
2261 azx_stop_chip(chip);
2262 }
2263
2264 if (chip->irq >= 0)
2265 free_irq(chip->irq, (void*)chip);
2266 if (chip->msi)
2267 pci_disable_msi(chip->pci);
2268 if (chip->remap_addr)
2269 iounmap(chip->remap_addr);
2270
2271 if (chip->azx_dev) {
2272 for (i = 0; i < chip->num_streams; i++)
2273 if (chip->azx_dev[i].bdl.area)
2274 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2275 }
2276 if (chip->rb.area)
2277 snd_dma_free_pages(&chip->rb);
2278 if (chip->posbuf.area)
2279 snd_dma_free_pages(&chip->posbuf);
2280 pci_release_regions(chip->pci);
2281 pci_disable_device(chip->pci);
2282 kfree(chip->azx_dev);
2283 kfree(chip);
2284
2285 return 0;
2286}
2287
2288static int azx_dev_free(struct snd_device *device)
2289{
2290 return azx_free(device->device_data);
2291}
2292
2293/*
2294 * white/black-listing for position_fix
2295 */
2296static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2297 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
2298 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2299 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2300 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2301 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2302 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2303 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2304 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2305 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2306 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2307 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
2308 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2309 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2310 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2311 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2312 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2313 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2314 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2315 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
2316 {}
2317};
2318
2319static int __devinit check_position_fix(struct azx *chip, int fix)
2320{
2321 const struct snd_pci_quirk *q;
2322
2323 chip->via_dmapos_patch = 0;
2324
2325 switch (fix) {
2326 case POS_FIX_LPIB:
2327 case POS_FIX_POSBUF:
2328 return fix;
2329 }
2330
2331 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2332 if (q) {
2333 /* Note that this implicitly sets via_dmapos_patch to zero */
2334 printk(KERN_INFO
2335 "hda_intel: position_fix set to %d "
2336 "for device %04x:%04x\n",
2337 q->value, q->subvendor, q->subdevice);
2338 return q->value;
2339 }
2340
2341 /* Check VIA/ATI HD Audio Controller exist */
2342 switch (chip->driver_type) {
2343 case AZX_DRIVER_VIA:
2344 case AZX_DRIVER_ATI:
2345 chip->via_dmapos_patch = 1;
2346 /* Use link position directly, avoid any transfer problem. */
2347 return POS_FIX_LPIB;
2348 }
2349
2350 return POS_FIX_AUTO;
2351}
2352
2353/*
2354 * black-lists for probe_mask
2355 */
2356static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2357 /* Thinkpad often breaks the controller communication when accessing
2358 * to the non-working (or non-existing) modem codec slot.
2359 */
2360 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2361 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2362 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2363 /* broken BIOS */
2364 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2365 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2366 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2367 /* forced codec slots */
2368 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2369 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2370 {}
2371};
2372
2373#define AZX_FORCE_CODEC_MASK 0x100
2374
2375static void __devinit check_probe_mask(struct azx *chip, int dev)
2376{
2377 const struct snd_pci_quirk *q;
2378
2379 chip->codec_probe_mask = probe_mask[dev];
2380 if (chip->codec_probe_mask == -1) {
2381 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2382 if (q) {
2383 printk(KERN_INFO
2384 "hda_intel: probe_mask set to 0x%x "
2385 "for device %04x:%04x\n",
2386 q->value, q->subvendor, q->subdevice);
2387 chip->codec_probe_mask = q->value;
2388 }
2389 }
2390
2391 /* check forced option */
2392 if (chip->codec_probe_mask != -1 &&
2393 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2394 chip->codec_mask = chip->codec_probe_mask & 0xff;
2395 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2396 chip->codec_mask);
2397 }
2398}
2399
2400/*
2401 * white/black-list for enable_msi
2402 */
2403static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2404 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2405 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2406 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2407 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2408 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2409 {}
2410};
2411
2412static void __devinit check_msi(struct azx *chip)
2413{
2414 const struct snd_pci_quirk *q;
2415
2416 if (enable_msi >= 0) {
2417 chip->msi = !!enable_msi;
2418 return;
2419 }
2420 chip->msi = 1; /* enable MSI as default */
2421 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2422 if (q) {
2423 printk(KERN_INFO
2424 "hda_intel: msi for device %04x:%04x set to %d\n",
2425 q->subvendor, q->subdevice, q->value);
2426 chip->msi = q->value;
2427 return;
2428 }
2429
2430 /* NVidia chipsets seem to cause troubles with MSI */
2431 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2432 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2433 chip->msi = 0;
2434 }
2435}
2436
2437
2438/*
2439 * constructor
2440 */
2441static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2442 int dev, int driver_type,
2443 struct azx **rchip)
2444{
2445 struct azx *chip;
2446 int i, err;
2447 unsigned short gcap;
2448 static struct snd_device_ops ops = {
2449 .dev_free = azx_dev_free,
2450 };
2451
2452 *rchip = NULL;
2453
2454 err = pci_enable_device(pci);
2455 if (err < 0)
2456 return err;
2457
2458 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2459 if (!chip) {
2460 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2461 pci_disable_device(pci);
2462 return -ENOMEM;
2463 }
2464
2465 spin_lock_init(&chip->reg_lock);
2466 mutex_init(&chip->open_mutex);
2467 chip->card = card;
2468 chip->pci = pci;
2469 chip->irq = -1;
2470 chip->driver_type = driver_type;
2471 check_msi(chip);
2472 chip->dev_index = dev;
2473 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2474
2475 chip->position_fix[0] = chip->position_fix[1] =
2476 check_position_fix(chip, position_fix[dev]);
2477 check_probe_mask(chip, dev);
2478
2479 chip->single_cmd = single_cmd;
2480
2481 if (bdl_pos_adj[dev] < 0) {
2482 switch (chip->driver_type) {
2483 case AZX_DRIVER_ICH:
2484 case AZX_DRIVER_PCH:
2485 bdl_pos_adj[dev] = 1;
2486 break;
2487 default:
2488 bdl_pos_adj[dev] = 32;
2489 break;
2490 }
2491 }
2492
2493#if BITS_PER_LONG != 64
2494 /* Fix up base address on ULI M5461 */
2495 if (chip->driver_type == AZX_DRIVER_ULI) {
2496 u16 tmp3;
2497 pci_read_config_word(pci, 0x40, &tmp3);
2498 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2499 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2500 }
2501#endif
2502
2503 err = pci_request_regions(pci, "ICH HD audio");
2504 if (err < 0) {
2505 kfree(chip);
2506 pci_disable_device(pci);
2507 return err;
2508 }
2509
2510 chip->addr = pci_resource_start(pci, 0);
2511 chip->remap_addr = pci_ioremap_bar(pci, 0);
2512 if (chip->remap_addr == NULL) {
2513 snd_printk(KERN_ERR SFX "ioremap error\n");
2514 err = -ENXIO;
2515 goto errout;
2516 }
2517
2518 if (chip->msi)
2519 if (pci_enable_msi(pci) < 0)
2520 chip->msi = 0;
2521
2522 if (azx_acquire_irq(chip, 0) < 0) {
2523 err = -EBUSY;
2524 goto errout;
2525 }
2526
2527 pci_set_master(pci);
2528 synchronize_irq(chip->irq);
2529
2530 gcap = azx_readw(chip, GCAP);
2531 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2532
2533 /* disable SB600 64bit support for safety */
2534 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2535 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2536 struct pci_dev *p_smbus;
2537 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2538 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2539 NULL);
2540 if (p_smbus) {
2541 if (p_smbus->revision < 0x30)
2542 gcap &= ~ICH6_GCAP_64OK;
2543 pci_dev_put(p_smbus);
2544 }
2545 }
2546
2547 /* disable 64bit DMA address for Teradici */
2548 /* it does not work with device 6549:1200 subsys e4a2:040b */
2549 if (chip->driver_type == AZX_DRIVER_TERA)
2550 gcap &= ~ICH6_GCAP_64OK;
2551
2552 /* allow 64bit DMA address if supported by H/W */
2553 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2554 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2555 else {
2556 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2557 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2558 }
2559
2560 /* read number of streams from GCAP register instead of using
2561 * hardcoded value
2562 */
2563 chip->capture_streams = (gcap >> 8) & 0x0f;
2564 chip->playback_streams = (gcap >> 12) & 0x0f;
2565 if (!chip->playback_streams && !chip->capture_streams) {
2566 /* gcap didn't give any info, switching to old method */
2567
2568 switch (chip->driver_type) {
2569 case AZX_DRIVER_ULI:
2570 chip->playback_streams = ULI_NUM_PLAYBACK;
2571 chip->capture_streams = ULI_NUM_CAPTURE;
2572 break;
2573 case AZX_DRIVER_ATIHDMI:
2574 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2575 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2576 break;
2577 case AZX_DRIVER_GENERIC:
2578 default:
2579 chip->playback_streams = ICH6_NUM_PLAYBACK;
2580 chip->capture_streams = ICH6_NUM_CAPTURE;
2581 break;
2582 }
2583 }
2584 chip->capture_index_offset = 0;
2585 chip->playback_index_offset = chip->capture_streams;
2586 chip->num_streams = chip->playback_streams + chip->capture_streams;
2587 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2588 GFP_KERNEL);
2589 if (!chip->azx_dev) {
2590 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2591 goto errout;
2592 }
2593
2594 for (i = 0; i < chip->num_streams; i++) {
2595 /* allocate memory for the BDL for each stream */
2596 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2597 snd_dma_pci_data(chip->pci),
2598 BDL_SIZE, &chip->azx_dev[i].bdl);
2599 if (err < 0) {
2600 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2601 goto errout;
2602 }
2603 }
2604 /* allocate memory for the position buffer */
2605 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2606 snd_dma_pci_data(chip->pci),
2607 chip->num_streams * 8, &chip->posbuf);
2608 if (err < 0) {
2609 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2610 goto errout;
2611 }
2612 /* allocate CORB/RIRB */
2613 err = azx_alloc_cmd_io(chip);
2614 if (err < 0)
2615 goto errout;
2616
2617 /* initialize streams */
2618 azx_init_stream(chip);
2619
2620 /* initialize chip */
2621 azx_init_pci(chip);
2622 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2623
2624 /* codec detection */
2625 if (!chip->codec_mask) {
2626 snd_printk(KERN_ERR SFX "no codecs found!\n");
2627 err = -ENODEV;
2628 goto errout;
2629 }
2630
2631 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2632 if (err <0) {
2633 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2634 goto errout;
2635 }
2636
2637 strcpy(card->driver, "HDA-Intel");
2638 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2639 sizeof(card->shortname));
2640 snprintf(card->longname, sizeof(card->longname),
2641 "%s at 0x%lx irq %i",
2642 card->shortname, chip->addr, chip->irq);
2643
2644 *rchip = chip;
2645 return 0;
2646
2647 errout:
2648 azx_free(chip);
2649 return err;
2650}
2651
2652static void power_down_all_codecs(struct azx *chip)
2653{
2654#ifdef CONFIG_SND_HDA_POWER_SAVE
2655 /* The codecs were powered up in snd_hda_codec_new().
2656 * Now all initialization done, so turn them down if possible
2657 */
2658 struct hda_codec *codec;
2659 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2660 snd_hda_power_down(codec);
2661 }
2662#endif
2663}
2664
2665static int __devinit azx_probe(struct pci_dev *pci,
2666 const struct pci_device_id *pci_id)
2667{
2668 static int dev;
2669 struct snd_card *card;
2670 struct azx *chip;
2671 int err;
2672
2673 if (dev >= SNDRV_CARDS)
2674 return -ENODEV;
2675 if (!enable[dev]) {
2676 dev++;
2677 return -ENOENT;
2678 }
2679
2680 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2681 if (err < 0) {
2682 snd_printk(KERN_ERR SFX "Error creating card!\n");
2683 return err;
2684 }
2685
2686 /* set this here since it's referred in snd_hda_load_patch() */
2687 snd_card_set_dev(card, &pci->dev);
2688
2689 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2690 if (err < 0)
2691 goto out_free;
2692 card->private_data = chip;
2693
2694#ifdef CONFIG_SND_HDA_INPUT_BEEP
2695 chip->beep_mode = beep_mode[dev];
2696#endif
2697
2698 /* create codec instances */
2699 err = azx_codec_create(chip, model[dev]);
2700 if (err < 0)
2701 goto out_free;
2702#ifdef CONFIG_SND_HDA_PATCH_LOADER
2703 if (patch[dev]) {
2704 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2705 patch[dev]);
2706 err = snd_hda_load_patch(chip->bus, patch[dev]);
2707 if (err < 0)
2708 goto out_free;
2709 }
2710#endif
2711 if ((probe_only[dev] & 1) == 0) {
2712 err = azx_codec_configure(chip);
2713 if (err < 0)
2714 goto out_free;
2715 }
2716
2717 /* create PCM streams */
2718 err = snd_hda_build_pcms(chip->bus);
2719 if (err < 0)
2720 goto out_free;
2721
2722 /* create mixer controls */
2723 err = azx_mixer_create(chip);
2724 if (err < 0)
2725 goto out_free;
2726
2727 err = snd_card_register(card);
2728 if (err < 0)
2729 goto out_free;
2730
2731 pci_set_drvdata(pci, card);
2732 chip->running = 1;
2733 power_down_all_codecs(chip);
2734 azx_notifier_register(chip);
2735
2736 dev++;
2737 return err;
2738out_free:
2739 snd_card_free(card);
2740 return err;
2741}
2742
2743static void __devexit azx_remove(struct pci_dev *pci)
2744{
2745 snd_card_free(pci_get_drvdata(pci));
2746 pci_set_drvdata(pci, NULL);
2747}
2748
2749/* PCI IDs */
2750static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2751 /* ICH 6..10 */
2752 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2753 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2754 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2755 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2756 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2757 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2758 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2759 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2760 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2761 /* PCH */
2762 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2763 { PCI_DEVICE(0x8086, 0x3b57), .driver_data = AZX_DRIVER_ICH },
2764 /* CPT */
2765 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2766 /* SCH */
2767 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2768 /* ATI SB 450/600 */
2769 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2770 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2771 /* ATI HDMI */
2772 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2773 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2774 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2775 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2776 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2777 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2778 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2779 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2780 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2781 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2782 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2783 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2784 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2785 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2786 /* VIA VT8251/VT8237A */
2787 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2788 /* SIS966 */
2789 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2790 /* ULI M5461 */
2791 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2792 /* NVIDIA MCP */
2793 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2794 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2795 .class_mask = 0xffffff,
2796 .driver_data = AZX_DRIVER_NVIDIA },
2797 /* Teradici */
2798 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2799 /* Creative X-Fi (CA0110-IBG) */
2800#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2801 /* the following entry conflicts with snd-ctxfi driver,
2802 * as ctxfi driver mutates from HD-audio to native mode with
2803 * a special command sequence.
2804 */
2805 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2806 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2807 .class_mask = 0xffffff,
2808 .driver_data = AZX_DRIVER_GENERIC },
2809#else
2810 /* this entry seems still valid -- i.e. without emu20kx chip */
2811 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2812#endif
2813 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2814 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2815 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2816 .class_mask = 0xffffff,
2817 .driver_data = AZX_DRIVER_GENERIC },
2818 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2819 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2820 .class_mask = 0xffffff,
2821 .driver_data = AZX_DRIVER_GENERIC },
2822 { 0, }
2823};
2824MODULE_DEVICE_TABLE(pci, azx_ids);
2825
2826/* pci_driver definition */
2827static struct pci_driver driver = {
2828 .name = "HDA Intel",
2829 .id_table = azx_ids,
2830 .probe = azx_probe,
2831 .remove = __devexit_p(azx_remove),
2832#ifdef CONFIG_PM
2833 .suspend = azx_suspend,
2834 .resume = azx_resume,
2835#endif
2836};
2837
2838static int __init alsa_card_azx_init(void)
2839{
2840 return pci_register_driver(&driver);
2841}
2842
2843static void __exit alsa_card_azx_exit(void)
2844{
2845 pci_unregister_driver(&driver);
2846}
2847
2848module_init(alsa_card_azx_init)
2849module_exit(alsa_card_azx_exit)
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-20 15:30:40 +0000